// +build f746xx

// Peripheral: USB_OTG_Device_Periph  USB_OTG_device_Registers.
// Instances:
// Registers:
//  0x00 32  DCFG       dev Configuration Register   800h.
//  0x04 32  DCTL       dev Control Register         804h.
//  0x08 32  DSTS       dev Status Register (RO)     808h.
//  0x10 32  DIEPMSK    dev IN Endpoint Mask         810h.
//  0x14 32  DOEPMSK    dev OUT Endpoint Mask        814h.
//  0x18 32  DAINT      dev All Endpoints Itr Reg    818h.
//  0x1C 32  DAINTMSK   dev All Endpoints Itr Mask   81Ch.
//  0x28 32  DVBUSDIS   dev VBUS discharge Register  828h.
//  0x2C 32  DVBUSPULSE dev VBUS Pulse Register      82Ch.
//  0x30 32  DTHRCTL    dev threshold                830h.
//  0x34 32  DIEPEMPMSK dev empty msk                834h.
//  0x38 32  DEACHINT   dedicated EP interrupt       838h.
//  0x3C 32  DEACHMSK   dedicated EP msk             83Ch.
//  0x44 32  DINEP1MSK  dedicated EP mask            844h.
//  0x84 32  DOUTEP1MSK dedicated EP msk             884h.
// Import:
//  stm32/o/f746xx/mmap
package usb

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	DSPD        DCFG = 0x03 << 0  //+ Device speed.
	DSPD_0      DCFG = 0x01 << 0  //  Bit 0.
	DSPD_1      DCFG = 0x02 << 0  //  Bit 1.
	NZLSOHSK    DCFG = 0x01 << 2  //+ Nonzero-length status OUT handshake.
	DAD         DCFG = 0x7F << 4  //+ Device address.
	DAD_0       DCFG = 0x01 << 4  //  Bit 0.
	DAD_1       DCFG = 0x02 << 4  //  Bit 1.
	DAD_2       DCFG = 0x04 << 4  //  Bit 2.
	DAD_3       DCFG = 0x08 << 4  //  Bit 3.
	DAD_4       DCFG = 0x10 << 4  //  Bit 4.
	DAD_5       DCFG = 0x20 << 4  //  Bit 5.
	DAD_6       DCFG = 0x40 << 4  //  Bit 6.
	PFIVL       DCFG = 0x03 << 11 //+ Periodic (micro)frame interval.
	PFIVL_0     DCFG = 0x01 << 11 //  Bit 0.
	PFIVL_1     DCFG = 0x02 << 11 //  Bit 1.
	PERSCHIVL   DCFG = 0x03 << 24 //+ Periodic scheduling interval.
	PERSCHIVL_0 DCFG = 0x01 << 24 //  Bit 0.
	PERSCHIVL_1 DCFG = 0x02 << 24 //  Bit 1.
)

const (
	DSPDn      = 0
	NZLSOHSKn  = 2
	DADn       = 4
	PFIVLn     = 11
	PERSCHIVLn = 24
)

const (
	RWUSIG   DCTL = 0x01 << 0  //+ Remote wakeup signaling.
	SDIS     DCTL = 0x01 << 1  //+ Soft disconnect.
	GINSTS   DCTL = 0x01 << 2  //+ Global IN NAK status.
	GONSTS   DCTL = 0x01 << 3  //+ Global OUT NAK status.
	TCTL     DCTL = 0x07 << 4  //+ Test control.
	TCTL_0   DCTL = 0x01 << 4  //  Bit 0.
	TCTL_1   DCTL = 0x02 << 4  //  Bit 1.
	TCTL_2   DCTL = 0x04 << 4  //  Bit 2.
	SGINAK   DCTL = 0x01 << 7  //+ Set global IN NAK.
	CGINAK   DCTL = 0x01 << 8  //+ Clear global IN NAK.
	SGONAK   DCTL = 0x01 << 9  //+ Set global OUT NAK.
	CGONAK   DCTL = 0x01 << 10 //+ Clear global OUT NAK.
	POPRGDNE DCTL = 0x01 << 11 //+ Power-on programming done.
)

const (
	RWUSIGn   = 0
	SDISn     = 1
	GINSTSn   = 2
	GONSTSn   = 3
	TCTLn     = 4
	SGINAKn   = 7
	CGINAKn   = 8
	SGONAKn   = 9
	CGONAKn   = 10
	POPRGDNEn = 11
)

const (
	SUSPSTS   DSTS = 0x01 << 0   //+ Suspend status.
	ENUMSPD   DSTS = 0x03 << 1   //+ Enumerated speed.
	ENUMSPD_0 DSTS = 0x01 << 1   //  Bit 0.
	ENUMSPD_1 DSTS = 0x02 << 1   //  Bit 1.
	EERR      DSTS = 0x01 << 3   //+ Erratic error.
	FNSOF     DSTS = 0x3FFF << 8 //+ Frame number of the received SOF.
)

const (
	SUSPSTSn = 0
	ENUMSPDn = 1
	EERRn    = 3
	FNSOFn   = 8
)

const (
	XFRCM     DIEPMSK = 0x01 << 0 //+ Transfer completed interrupt mask.
	EPDM      DIEPMSK = 0x01 << 1 //+ Endpoint disabled interrupt mask.
	TOM       DIEPMSK = 0x01 << 3 //+ Timeout condition mask (nonisochronous endpoints).
	ITTXFEMSK DIEPMSK = 0x01 << 4 //+ IN token received when TxFIFO empty mask.
	INEPNMM   DIEPMSK = 0x01 << 5 //+ IN token received with EP mismatch mask.
	INEPNEM   DIEPMSK = 0x01 << 6 //+ IN endpoint NAK effective mask.
	TXFURM    DIEPMSK = 0x01 << 8 //+ FIFO underrun mask.
	BIM       DIEPMSK = 0x01 << 9 //+ BNA interrupt mask.
)

const (
	XFRCMn     = 0
	EPDMn      = 1
	TOMn       = 3
	ITTXFEMSKn = 4
	INEPNMMn   = 5
	INEPNEMn   = 6
	TXFURMn    = 8
	BIMn       = 9
)

const (
	XFRCM    DOEPMSK = 0x01 << 0 //+ Transfer completed interrupt mask.
	EPDM     DOEPMSK = 0x01 << 1 //+ Endpoint disabled interrupt mask.
	STUPM    DOEPMSK = 0x01 << 3 //+ SETUP phase done mask.
	OTEPDM   DOEPMSK = 0x01 << 4 //+ OUT token received when endpoint disabled mask.
	OTEPSPRM DOEPMSK = 0x01 << 5 //+ Status Phase Received mask.
	B2BSTUP  DOEPMSK = 0x01 << 6 //+ Back-to-back SETUP packets received mask.
	OPEM     DOEPMSK = 0x01 << 8 //+ OUT packet error mask.
	BOIM     DOEPMSK = 0x01 << 9 //+ BNA interrupt mask.
)

const (
	XFRCMn    = 0
	EPDMn     = 1
	STUPMn    = 3
	OTEPDMn   = 4
	OTEPSPRMn = 5
	B2BSTUPn  = 6
	OPEMn     = 8
	BOIMn     = 9
)

const (
	IEPINT DAINT = 0xFFFF << 0  //+ IN endpoint interrupt bits.
	OEPINT DAINT = 0xFFFF << 16 //+ OUT endpoint interrupt bits.
)

const (
	IEPINTn = 0
	OEPINTn = 16
)

const (
	IEPM DAINTMSK = 0xFFFF << 0  //+ IN EP interrupt mask bits.
	OEPM DAINTMSK = 0xFFFF << 16 //+ OUT EP interrupt mask bits.
)

const (
	IEPMn = 0
	OEPMn = 16
)

const (
	VBUSDT DVBUSDIS = 0xFFFF << 0 //+ Device VBUS discharge time.
)

const (
	VBUSDTn = 0
)

const (
	DVBUSP DVBUSPULSE = 0xFFF << 0 //+ Device VBUS pulsing time.
)

const (
	DVBUSPn = 0
)

const (
	NONISOTHREN DTHRCTL = 0x01 << 0   //+ Nonisochronous IN endpoints threshold enable.
	ISOTHREN    DTHRCTL = 0x01 << 1   //+ ISO IN endpoint threshold enable.
	TXTHRLEN    DTHRCTL = 0x1FF << 2  //+ Transmit threshold length.
	TXTHRLEN_0  DTHRCTL = 0x01 << 2   //  Bit 0.
	TXTHRLEN_1  DTHRCTL = 0x02 << 2   //  Bit 1.
	TXTHRLEN_2  DTHRCTL = 0x04 << 2   //  Bit 2.
	TXTHRLEN_3  DTHRCTL = 0x08 << 2   //  Bit 3.
	TXTHRLEN_4  DTHRCTL = 0x10 << 2   //  Bit 4.
	TXTHRLEN_5  DTHRCTL = 0x20 << 2   //  Bit 5.
	TXTHRLEN_6  DTHRCTL = 0x40 << 2   //  Bit 6.
	TXTHRLEN_7  DTHRCTL = 0x80 << 2   //  Bit 7.
	TXTHRLEN_8  DTHRCTL = 0x100 << 2  //  Bit 8.
	RXTHREN     DTHRCTL = 0x01 << 16  //+ Receive threshold enable.
	RXTHRLEN    DTHRCTL = 0x1FF << 17 //+ Receive threshold length.
	RXTHRLEN_0  DTHRCTL = 0x01 << 17  //  Bit 0.
	RXTHRLEN_1  DTHRCTL = 0x02 << 17  //  Bit 1.
	RXTHRLEN_2  DTHRCTL = 0x04 << 17  //  Bit 2.
	RXTHRLEN_3  DTHRCTL = 0x08 << 17  //  Bit 3.
	RXTHRLEN_4  DTHRCTL = 0x10 << 17  //  Bit 4.
	RXTHRLEN_5  DTHRCTL = 0x20 << 17  //  Bit 5.
	RXTHRLEN_6  DTHRCTL = 0x40 << 17  //  Bit 6.
	RXTHRLEN_7  DTHRCTL = 0x80 << 17  //  Bit 7.
	RXTHRLEN_8  DTHRCTL = 0x100 << 17 //  Bit 8.
	ARPEN       DTHRCTL = 0x01 << 27  //+ Arbiter parking enable.
)

const (
	NONISOTHRENn = 0
	ISOTHRENn    = 1
	TXTHRLENn    = 2
	RXTHRENn     = 16
	RXTHRLENn    = 17
	ARPENn       = 27
)

const (
	INEPTXFEM DIEPEMPMSK = 0xFFFF << 0 //+ IN EP Tx FIFO empty interrupt mask bits.
)

const (
	INEPTXFEMn = 0
)

const (
	IEP1INT DEACHINT = 0x01 << 1  //+ IN endpoint 1interrupt bit.
	OEP1INT DEACHINT = 0x01 << 17 //+ OUT endpoint 1 interrupt bit.
)

const (
	IEP1INTn = 1
	OEP1INTn = 17
)
